In post-65 nm generation microscopic technology for a large-scale integrated circuit designed by a gate array method or a standard cell method used in an information processing device, there is known a technique for increasing the mobility of electron and holes by using a dual-stress called strained silicon in the drain-source portion. Further, in the case where a plurality of circuits are arranged close to one another, an STI (Shallow Trench Isolation) is used for device isolation, in which a trench is formed in a silicon surface by anisotropic etching, and the trench is buried with an insulating film such as an oxide film, followed by flattening.
As a prior art relating to the present invention, there is known a CMOS (Complementary Metal Oxide Semiconductor) in which a shield gate is provided between NMOS (Negative channel Metal Oxide Semiconductor) transistors and an active region provided for each PMOS (Positive channel Metal Oxide Semiconductor) transistor (refer to, e.g., Patent Document 1).    [Patent Document 1] Japanese Laid-Open Patent Publication No. 2006-210453